ISL12023
23
FN6682.3
December 6, 2011
operation. The master must respond with an ACK after receiving
a Data Byte of a read operation.
Device Addressing
Following a start condition, the master must output a Slave Address
Byte. The 7 MSBs are the device identifier. These bits are “1101111”
for the RTC registers and 1010111” for the User SRAM.
The last bit of the Slave Address Byte defines a read or write
operation to be performed. When this R/W bit is a “1”, then a read
operation is selected. A “0” selects a write operation (refer to
Figure 17).
.
FIGURE 14. VALID DATA CHANGES, START AND STOP CONDITIONS
FIGURE 15. ACKNOWLEDGE RESPONSE FROM RECEIVER
FIGURE 16. BYTE WRITE SEQUENCE (SLAVE ADDRESS FOR CSR SHOWN)
SDA
SCL
START
DATA
STOP
STABLE
CHANGE
DATA
STABLE
SDA OUTPUT FROM
TRANSMITTER
SDA OUTPUT FROM
RECEIVER
8
1
9
START
ACK
SCL FROM
MASTER
HIGH IMPEDANCE
S
T
A
R
T
S
T
O
P
IDENTIFICATION
BYTE
DATA
BYTE
A
C
K
SIGNALS FROM
THE MASTER
SIGNALS FROM
THE ISL12023
A
C
K
10
0
11
A
C
K
WRITE
SIGNAL AT SDA
00 00
11 1
ADDRESS
BYTE
FIGURE 17. SLAVE ADDRESS, WORD ADDRESS, AND DATA BYTES
SLAVE
ADDRESS BYTE
D7
D6
D5
D2
D4
D3
D1
D0
A0
A7
A2
A4
A3
A1
DATA BYTE
A6
A5
1
10
1
R/W
1
WORD ADDRESS
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